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Lattice Semiconductor
Register Descriptions
MODE (R/W)
Mnemonic: MODE
POR Value = 0000H
Functional Description
Name
Rsvd
Tx_en
Rx_en
FC_en
Gbit_en
Range
15:4
3
2
1
0
Description
Reserved .
Transmit Enable . When this bit is set, the Tx MAC is enabled to transmit frames. When
reset, the Tx MAC completes transmission of the packet currently being processed, then
stops.
Receive Enable . When this bit is set, the Rx MAC is enabled to receive frames. When
reset, the Rx MAC completes reception of the packet currently being processed, then
stops.
Flow-control Enable . When set, this bit enables the flow control functionality of the Tx
MAC. This bit should be set to enable the Tx MAC to transmit a PAUSE frame via the
tx_sndpausreq and tx_sndpaustim[15:0] MAC input ports.
Gigabit Enable . For the Classic Tri-speed MAC option, in order to operate in GbE mode,
this bit must be set high. For 10/100 mode, this bit must be set low.
For the SGMII Easy Connect MAC option, this bit does not control anything (note the MAC
operation speed is determined by the clock enables provided by the SGMII IP core). This
bit will echo back what is written to it.
For the Gigabit MAC option, this bit is a read-only bit and will always read back as logic
high. This bit does not control anything in the core.
Note, the state of this bit is useful for system use, since the cpu_if_gbit_en output signal,
from the core, always reflects the state of this register bit.
IPUG51_03.0, December 2010
26
Tri-Speed Ethernet MAC User’s Guide
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